1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a formation of a salicide for a semiconductor device.
2. Description of the Related Art
As semiconductor devices advance in operation speed, some of their elements, for example, gate resistance of a MOS device, contact resistance of the source and drain region serve as factors to cause the operation speed of the semiconductor devices to be slow. To prevent the operation speed from being slow, a method of forming a salicide layer on gate, source and drain regions has been widely used.
A method of manufacturing a semiconductor device according to the related art will now be described with reference to FIGS. 1A to 1C.
Referring to FIG. 1A, the related art semiconductor device includes a substrate 10 having a device isolation layer 11. A gate insulating layer 12 is formed on the substrate 10 and a gate 13 is formed on the gate insulating layer 12.
Next, an oxide layer 16 and a nitride layer 17 are sequentially formed on an entire surface of the substrate 10 so as to cover the gate 13. Then, the nitride layer 17 is etched back to form a nitride spacer on both sidewalls of the gate 13. Thereafter, impurity ions having an opposite conductivity type to the substrate 10 are implanted at a high concentration into the substrate 10 to form a source region 18′ and a drain region 18 at both sides of the gate 13 in the substrate 10.
At this time, oxygen 100 penetrates into the surfaces of source region 18′, the drain region 18 and the gate 13 and remains thereon.
Next, referring to FIG. 1B, the oxide layer 16 on the gate 13 and the substrate 10 is removed to expose the surfaces of the gate 13, the source region 18′ and the drain region 18.
Next, referring to FIG. 1C, a metal layer is deposited on the exposed surfaces of the source region 18′, the drain region 18 and the gate 13, and is then thermally annealed to form a salicide layer 19.
However, in the related art semiconductor device, since the impurity ions for the formation of the source region 18′ and the drain region 18 are implanted at a high concentration, if the oxide layer 16 remains on the surface of the substrate 10, an oxygen knock-on effect in which oxygen 100 of the oxide layer 16 penetrates into the surfaces of the source region 18′, the drain region 18 and the gate together with the impurities may occur.
Thus, the oxygen 100 penetrating into the surfaces of the source region 18′, the drain region 18 and the gate 13 is not completely removed but remains thereon even after the oxide layer 16 is removed. The remaining oxygen 100 prevents a salicide from being formed during the subsequent salicide process, so that an instable and non-uniform salicide layer 19 is formed to increase the resistances of the gate 13, the source region 18′ and the drain region 18, as shown in FIG. 1C.
In addition, if the oxide 16 is over-etched so as to solve the oxygen knock-on effect, the oxygen 100 on the surfaces of the gate 13, the source region 18′ and the drain region 18 is partially removed, but another problem, such as a reverse narrow width effect in which the threshold voltage is dropped at a boundary (A) between the device isolation layer 11 and the active region due to an excessive loss of the insulating layer, occurs.